YAP
7.1.0
locks_sparc.h
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/************************************************************************
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** **
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** The YapTab/YapOr/OPTYap systems **
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** **
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** YapTab extends the Yap Prolog engine to support sequential tabling **
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** YapOr extends the Yap Prolog engine to support or-parallelism **
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** OPTYap extends the Yap Prolog engine to support or-parallel tabling **
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** **
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** **
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** Yap Prolog was developed at University of Porto, Portugal **
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** **
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************************************************************************/
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/************************************************************************
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** Atomic locks for SPARC **
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************************************************************************/
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#define swap_il(adr,reg) \
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({ int _ret; \
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asm volatile ("swap %1,%0"
\
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: "=r" (_ret), "=m" (*(adr))
/* Output %0,%1 */
\
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: "m"
(*(adr)), "0" (reg));
/* Input (%2),%0 */
\
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_ret; \
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})
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#define TRY_LOCK(LOCK_VAR) (swap_il((LOCK_VAR),1)==0)
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#define INIT_LOCK(LOCK_VAR) ((LOCK_VAR) = 0)
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#define LOCK(LOCK_VAR) do { \
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if (TRY_LOCK(&(LOCK_VAR))) break; \
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while (IS_LOCKED(LOCK_VAR)) continue; \
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} while (1)
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#define IS_LOCKED(LOCK_VAR) ((LOCK_VAR) != 0)
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#define IS_UNLOCKED(LOCK_VAR) ((LOCK_VAR) == 0)
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#define UNLOCK(LOCK_VAR) ((LOCK_VAR) = 0)
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/* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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*/
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typedef
struct
{
volatile
unsigned
int
lock; }
rwlock_t
;
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/* Sort of like atomic_t's on Sparc, but even more clever.
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*
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* ------------------------------------
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* | 24-bit counter | wlock | rwlock_t
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* ------------------------------------
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* 31 8 7 0
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*
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* wlock signifies the one writer is in or somebody is updating
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* counter. For a writer, if he successfully acquires the wlock,
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* but counter is non-zero, he has to release the lock and wait,
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* till both counter and wlock are zero.
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*
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* Unfortunately this scheme limits us to ~16,000,000 cpus.
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*/
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static
__inline__
void
_read_lock(
rwlock_t
*rw)
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{
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register
rwlock_t
*lp
asm
(
"g1"
);
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lp = rw;
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asm
__volatile__(
"mov %%o7, %%g4\n\t"
\
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"call ___rw_read_enter\n\t"
\
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"ldstub [%%g1 + 3], %%g2\n"
\
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:
/* no outputs */
\
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:
"r"
(lp) \
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:
"g2"
,
"g4"
,
"g7"
,
"memory"
,
"cc"
);
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}
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#define READ_LOCK(lock) \
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do { _read_lock(&(lock)); \
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} while(0)
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static
__inline__
void
_read_unlock(
rwlock_t
*rw)
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{
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register
rwlock_t
*lp
asm
(
"g1"
);
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lp = rw;
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asm
__volatile__( \
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"mov %%o7, %%g4\n\t"
\
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"call ___rw_read_exit\n\t"
\
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"ldstub [%%g1 + 3], %%g2\n"
\
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:
/* no outputs */
\
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:
"r"
(lp) \
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:
"g2"
,
"g4"
,
"g7"
,
"memory"
,
"cc"
);
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}
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#define READ_UNLOCK(lock) \
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do { _read_unlock(&lock); \
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} while(0)
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static
__inline__
void
write_lock(
rwlock_t
*rw)
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{
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register
rwlock_t
*lp
asm
(
"g1"
);
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lp = rw;
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asm
__volatile__( \
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"mov %%o7, %%g4\n\t"
\
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"call ___rw_write_enter\n\t"
\
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"ldstub [%%g1 + 3], %%g2\n\t"
\
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:
/* no outputs */
\
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:
"r"
(lp) \
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:
"g2"
,
"g4"
,
"g7"
,
"memory"
,
"cc"
);
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}
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#define WRITE_LOCK(X) write_lock(&(X))
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#define WRITE_UNLOCK(rw) do { (&(rw))->lock = 0; } while(0)
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#define INIT_RWLOCK(RW) (RW).lock = 0
rwlock_t
Definition:
locks_alpha.h:38
OPTYap
locks_sparc.h
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